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Timing Specifications
Write Mode
Table 10. Write Cycle Timing 1 (W Controlled) 1, 2, 3, 4, 5
Parameter
Symbol
Min
Max
Unit
Write cycle
time 6
t AVAV
35
—
ns
Address set-up time
Address valid to end of write (G high)
Address valid to end of write (G low)
Write pulse width (G high)
Write pulse width (G low)
Data valid to end of write
Data hold time
t AVWL
t AVWH
t AVWH
t WLWH
t WLEH
t WLWH
t WLEH
t DVWH
t WHDX
0
18
20
15
15
10
0
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
Write low to data Hi-Z
7, 8, 9
t WLQZ
0
12
ns
Write high to output
Write recovery time
active 7, 8, 9
t WHQX
t WHAX
3
12
—
—
ns
ns
NOTES:
10
1
2
3
4
5
6
7
8
9
A write occurs during the overlap of E low and W low.
Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and
bus contention conditions must be minimized or eliminated during read and write cycles.
If G goes low at the same time or after W goes low, the output will remain in a high-impedance state.
After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum
of 2 ns.
The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent
cycle is the same as the minimum cycle time allowed for the device.
All write cycle timings are referenced from the last valid address to the first transition address.
This parameter is sampled and not 100% tested.
Transition is measured ± 200 mV from steady-state voltage.
At any given voltage or temperature, t WLQZ max < t WHQX min.
MR2A16A Data Sheet, Rev. 6
Freescale Semiconductor
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